FIG. 1 schematically represents a classic double-point modulator, as described in U.S. patent application publication No. 2010/0066459. More particularly, the classic double-point modulator includes a phase-locked loop designed to synthetize the carrier frequency using a reference frequency Fref.
The loop comprises a voltage-controlled oscillator VCO producing a signal Fout, the central frequency of which is set to the desired carrier frequency. The signal Fout feeds a programmable divider DIV. A phase comparator 10 receives the reference frequency Fref and the output of the divider DIV. The output of the phase comparator 10 is provided as a setpoint of the oscillator VCO through a low-pass filter 12.
The carrier frequency is determined by a digital signal Fc provided to a sigma-delta modulator SDM, the output of which sets the average division ratio of the divider DIV. The output of the modulator SDM can be coded on one or more bits. If it is coded on one bit, this bit selects a division ratio of N or N+1, where N is an integer. Thus, the central frequency of the signal Fout can be chosen between NFref and (N+1)Fref. If the output of the modulator SDM is coded on several bits, these bits select one of several consecutive integers comprising N.
The “double-point” modulation is performed using two correlated modulation signals that respectively modulate the carrier frequency Fc setpoint at the input of the sigma-delta modulator SDM and the setpoint of the oscillator VCO at the output of the filter 12.
Originally, the modulation signal MW is digital. It is added by an adder 14 to the digital carrier Fc setpoint at the input of the sigma-delta modulator SDM. However, the oscillator VCO requires an analog control signal. Thus, a digital-to-analog converter DAC producing an analog modulation signal m from the signal MW is provided. The signal m is added by an adder 16 to the output of the filter 12 at the control input of the oscillator VCO.
In a simpler “single-point” modulator, the modulation signal only acts on the division ratio of the divider DIV. However, the bandwidth of the modulation is then limited by the low-pass filter 12, which is used to remove the high-frequency noise generated by the sigma-delta modulator.
The transfer function applied to the modulation seen from the divider DIV acts as a low-pass filter while that applied to the modulation seen from the converter DAC acts as a high-pass filter. If the sum of these two transfer functions is equal to a constant, the bandwidth of the modulator is infinite. This condition is achieved when the respective gains of the modulation paths passing through the divider DIV and the converter DAC are identical.
It may be desirable to therefore match the gains of the two paths. One difficulty lies in the fact that these paths are made up of functional elements of different nature. Another difficulty is that the path through the converter DAC is analog, whereas the one passing through the divider DIV is digital.
To address this difficulty, the abovementioned patent application suggests a control circuit CTRL which sets the gain of the analog modulation signal m during an open-loop calibration phase. The gain can be set by a signal g, which determines the reference of the digital-to-analog converter DAC.
During a calibration phase, determined by the activation of a signal Cal, the loop is opened using a selector switch S1 placed between the phase comparator 10 and the filter 12. The central frequency of the oscillator VCO is then fixed and determined by the value reached at the output of the filter 12, which remains stored in a capacitive element of the filter. The control circuit CTRL applies an initial gain g to the converter DAC, such as an average value preprogrammed in the circuit. Two calibration values of the digital modulation signal MW are applied successively. For each calibration value, the circuit CTRL measures the resulting frequency of the signal Fout. The circuit then calculates a new gain g according to the initial gain and to the ratio of the difference in the frequencies measured to the difference in the calibration values.
The frequency measurement is based on counting the number of pulses of the signal Fout over a sufficient number of periods of the signal Fref. Such a count produces an integer accurate to within one unit by default. If the accuracy is not satisfactory, the number of periods of the signal Fref over which pulses are counted could be increased. However, given that a calibration must generally be done every time the carrier frequency Fc changes, the calibration duration compared to the useful modulation duration would increase to an unacceptable extent in certain applications, particularly for Bluetooth transmission in which the carrier frequency changes regularly during use (“frequency hopping”).
To improve the accuracy while limiting the counting duration, the abovementioned patent application suggests a method for estimating the fractional part of the count using a decimation filter which calculates the average of counts over the periods of the signal Fref. The accuracy of this method depends on the number of periods of the signal Fref, and thus, on the counting duration.